1. Field of the Invention
The present invention relates to a SRAM, particularly to a disturb-free independently-controlled-gate FinFET SRAM.
2. Description of the Related Art
Memories, such as SRAM, are embedded in consumer electronics, communication electronics, microprocessors and various hardwares to store data. In the semiconductor industry, since the scaling of CMOS has reached the physical limit as the feature size reduced down to 20 nm, FinFET (Fin-based Field Effect Transistor) with the superiority gate-control, better SCE (short-channel-effect), Ion/Ioff ratio, subthreshold swing and RDF (Random Dopant Fluctuation) immunity has been proposed as the promising candidates for future generation memory devices. Among the embedded memories, SRAM (Static Random Access Memory) plays the most important role and occupies the highest proportion, thus by using FinFET-based SRAM can greatly reduce the size of IC chips and effectively decrease the power consumption of each logic gate.
Refer to FIG. 1, it shows a conventional 6T SRAM which comprises a plurality of memory cells and here is exemplified by the 6T SRAM device containing four memory cells 10a, 10b, 10c and 10d, all of which have an identical structure. The memory cell 10a is used to exemplify the abovementioned memory cells. The memory cell 10a has a first inverter 12, a second inverter 14, a first access transistor 28 and a second access transistor 30, wherein the first and second inverters 12 and 14 are cross coupled. The storage node 16 of the first inverter 12 is directly connected to the gates of a P-type transistor 18 and an N-type transistor 20 of the second inverter 14. The storage node 22 of the second inverter 14 is directly connected to the gates of a P-type transistor 24 and an N-type transistor 26 of the first inverter 12. The source of the N-type transistor 26 of the first inverter 12 is grounded. The source of the P-type transistor 24 of the first inverter 12 is connected to a voltage supply Vcs of the memory cell. The source of the N-type transistor 20 of the second inverter 14 is grounded. The source of the P-type transistor 18 of the second inverter 14 is connected to the voltage supply Vcs of the memory cell. There are at least two word lines, such as WL1 and WL2, connected to the cells in the horizontal row direction. For example, WL1 is connected with the first access transistors 28 and the second access transistors 30 of the memory cells 10a, 10b and cells arranged in the same horizontal row direction. WL2 is connected with the first access transistors 28 and the second access transistors 30 of the memory cells 10c, 10d and cells arranged in the same horizontal row direction. In writing data into or reading data from the storage node 16 of the first inverter 12, WL1 or WL2 is turned on to control the first access transistor 28 to enable write or read. The first access transistor 28 is connected to the bit line BL1 or BL2. In writing data into or reading data from the storage node 22 of the first inverter 14, WL1 or WL2 is turned on to control the second access transistor 30 to enable write or read. The second access transistor 30 is connected to the complementary bit line BR1 or BR2. The first and second access transistors 28 and 30 are controlled by a common word line WL1 or WL2. Below, the memory cell 10a is used as an example to explain the read/write behavior of a memory cell. Before read/write the memory cell 10a, BL1 and BR1 are pre-charged to a high voltage level “1”. When read/write the memory cell 10a, BL1 and BR1 are floating. Assume the data stored in the storage node 16 of the first inverter 12 is “0” and the data stored in the storage node 22 of the second inverter 14 is “1”. WL1 simultaneously turns on the first and second access transistors 28 and 30, thus via the discharging path of the N-type transistor 26 of the first inverter 12, BL1 is successfully discharged to ground, and meanwhile, BR1 is maintained at a high-level voltage, and the data is successfully read. However, the conventional 6T SRAM cell has two critical problems during read: First, the “half-select” problem, as WL1 simultaneously turns on the memory cells 10a, 10b, and cells arranged in the same horizontal row, there is current flowing in the memory cell 10b of which data is not read, and cause the bit line adjacent to the node stored “0” discharged or even flip the data; the flipped data causes a read error when the memory cell 10b is read later. Second, when both the first access transistor 28 and second access transistor 30 of the memory cell 10a are turned on, the first access transistor 28 and the N-type transistor 26 of the first inverter 12 form a voltage-divided path, and cause a “read disturb” voltage on the storage node 16 originally stored data “0”. The node voltage of the storage node 16 and the read disturb voltage is likely to exceed the trip voltage of the second inverter 14 at a low operation voltage, and cause the data stored in the second inverter 14 flipped, making a read error.
Refer to FIG. 2, it shows a 6T-column-decoupled SRAM, which was developed to solve the problem of read errors caused by leakage current and read disturb voltage of the abovementioned 6T SRAM operating in low operation voltage. Different to conventional 6T SRAM cell, a bit-select line is added to the memory cells arranged in the same vertical column in 6T-column-decoupled SRAM cell. As shown in FIG. 2, there are two bit-select lines BS1 and BS2. The memory cell 10a is used to exemplify the 6T-column-decoupled SRAM cell.
In 6T-column-decoupled cell, BS1 is connected to the back gates of the first access transistor 28 and the second access transistor 30, and WL1 is connected to the front gates of the first access transistor 28 and the second access transistor 30. During read, only the selected memory cell 10a, its front and back gates of the first access transistor 28 and the second access transistor 30 are turned on, thus solving the “half-select” problem mentioned in the conventional 6T SRAM. Nevertheless, WL1 turns on the front gates of the first access transistor 28 and the second access transistor 30 of the memory cell 10b in the horizontal row (WL1 direction), and BS1 turns on the back gates of the first access transistor 28 and the second access transistor 30 of the memory cell 10c in the vertical column (BS1 direction). The first access transistors 28 and the second access transistors 30 of the unselected memory cells 10b and 10c are only half turned on (i.e. the so-called half-select disturb), thus read behavior is not taken place in the unselected memory cells 10b and 10c. During read, only one of the gate of the first access transistor 28 and the second access transistor 30 of the unselected memory cell 10b in the horizontal row is turned on, thus the half-select disturb of the memory cell 10b can be mitigated compared with the 6T SRAM cell in FIG. 1. However, the scheme of FIG. 2 cannot yet solve the second problem in the scheme of FIG. 1: The read disturb may lower RSNM (Read Static Noise Margin) or even flip the stored data and thus limit the minimum operation voltage. Besides, the leakage current generated by a single turned-on gate would accumulatively discharge the voltage of the bit line BL1 or BL2 and thus causes a read error. In other words, the access transistors of the unselected memory cells in a half-turned on state due to the back gates of the access transistors are turned on, along with the increased number of the memory cells along a bit line, the leakage current generated by the half-turned on transistors may flip the data stored in the selected memory cell and causes a read error. Besides, the more serious process variation and intrinsic device variation faced in scaled devices may further limit the number of the cells arranged along one bit line.
Accordingly, the present invention proposes a disturb-free independently-controlled-gate FinFET SRAM cell to overcome the abovementioned problems.